1. Field of the Invention
The present invention relates to a semiconductor logic circuit, and more particularly to a Bi-CMOS logic circuit of the type in which bipolar (Bi) elements and complementary oxide semiconductor (CMOS) elements are formed on a substrate.
2. Description of the Related Art
Recently, in manufacturing semiconductor logic circuits, for example, emphasis has been placed on how to integrate circuit elements at a high density in accordance with the scaling rule, so as to improve an operating speed of the integrated circuits. In the case of MOS transistors, attempts have been made on reducing the channel width and thinning the gate oxide film so as to integrate circuit elements at a high density and improve the operating speed of the integrated circuits. However, thinning of the gate oxide film results in a large voltage applied to the oxide film and therefore its reliability will not be assured over a long period. For this reason, it is required for microfabricated MOS transistors to lower the power source voltage before applied to the oxide film. This is not easily done because compatibility with other devices is required. One solution for the above problem is to use the internal power source voltage drop technique in which a voltage drop circuit is incorporated in the integrated circuit so as to obtain a low voltage and use it as an internal power source.
Let us consider a case where a Bi-CMOS inverter, for example, is used for an output system of a BI-CMOS semiconductor logic circuit containing such a power source voltage drop circuit. In such a circuit arrangement, improvement of an operating speed is made by driving the base current of the output buffer using a pair of bipolar transistors by using a CMOS element. Further, an external power source voltage is applied to the collector of a pull-up bipolar transistor of the paired ones. An internal power source supplied from the power source drop circuit is supplied to the source of the p-channel MOS transistor of the CMOS element.
In the Bi-CMOS inverter, the drain of the n-channel MOS transistor is directly connected to an output node Out. Because of this connection, there is the possibility that the external power source voltage is applied across the source-drain path. In this respect, reliability of the gate oxide film of the MOS transistor is not assured.
Where a Bi-CMOS inverter is used in the output system of the Bi-CMOS semiconductor logic circuit, some measure must be taken. One measure is to set the gate oxide film of the n-channel MOS transistor thicker than those of the other MO transistors in the manufacturing stage. This measure, however, needs an increase of the number of process steps. The increased number of process steps leads to reduction of a production yield, and increase of cost to manufacture.